The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 05, 2020
Filed:
Jan. 31, 2019
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Lisa R. McIlwain, Oregon City, OR (US);
Michael S. Quayle, Carlisle, MA (US);
Eyal Odiz, Los Altos Hill, CA (US);
Patrick Groeneveld, Saratoga, CA (US);
John W. Hagerman, Boxford, MA (US);
Kshama Jambhekar, Acton, MA (US);
Phillip W. Baraona, Somerville, MA (US);
Assignee:
Synopsys, Inc., Mountain View, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 17/50 (2006.01); G06F 30/327 (2020.01); G06F 30/3323 (2020.01);
U.S. Cl.
CPC ...
G06F 30/327 (2020.01); G06F 30/3323 (2020.01);
Abstract
Techniques and systems for concurrent formal verification of logic synthesis are described. A synthesis tool can write intermediate checkpoint designs that embody the state of an integrated circuit (IC) design under synthesis as optimization progresses. Meanwhile, formal equivalence checking proceeds in parallel with synthesis and checks the intermediate checkpoint designs for equivalence.