Patrick D Fortner

Title: The Innovations of Patrick D Fortner

Introduction

Patrick D Fortner is a notable inventor based in Beaverton, OR (US). He has made significant contributions to the field of integrated circuit design and static timing analysis. With a total of 4 patents to his name, Fortner's work has had a considerable impact on the industry.

Latest Patents

Among his latest patents is the "Recursive Hierarchical Static Timing Analysis." This method involves accessing a lower-level netlist representing a block of a circuit design and performing static timing analysis on it. The process also includes analyzing an upper-level netlist and incorporating results from the lower-level block's analysis. This recursive approach allows for updating constraints between the two levels, enhancing the accuracy of timing analysis.

Another significant patent is "Parallel Parasitic Processing in Static Timing Analysis." This technique describes a static timing analysis process that includes both a main and a parallel process. The main process involves loading an IC design and applying timing constraints, while the parallel process back-annotates interconnect parasitics onto the design. This innovative approach allows for concurrent processing, improving efficiency in timing updates.

Career Highlights

Fortner has worked with prominent companies in the industry, including Synopsys, Inc. and Mentor Graphics Corporation. His experience in these organizations has contributed to his expertise in integrated circuit design and timing analysis.

Collaborations

Throughout his career, Fortner has collaborated with talented individuals such as Qiuyang Wu and Florentin Dartu. These collaborations have likely enriched his work and led to further innovations in the field.

Conclusion

Patrick D Fortner's contributions to static timing analysis and integrated circuit design demonstrate his innovative spirit and technical expertise. His patents reflect a commitment to advancing technology in the industry.