Synopsys, Inc.

Mentor Graphics Corporation

Patrick D Fortner

Qiuyang Wu

Kayhan Kucukcakar

Florentin Dartu

Subramanyam Sripada

Jonathan Weiss

A method for recursive hierarchical static timing analysis. The method includes accessing a lower-level netlist representing a lower-level block of a circuit design to be realized in physical form, and accessing constraints for the lower-level block. Static timing analysis is performed on the lower-level block. The method includes accessing an upper-level netlist representing an upper-level block of the circuit design to be realized in physical form, and accessing constraints for the upper-level block. Static timing analysis is performed on the upper-level block while incorporating results from the static timing analysis on the lower-level block. Subsequently, recursive static timing analysis is performed on the lower-level block and the upper-level block, wherein results from static timing analysis on the upper-level block are feedback for updating the constraints for the lower-level block, and wherein results from static timing analysis on the lower-level block are feedback for updating the constraints for the upper-level block.

Recursive hierarchical static timing analysis

A static timing analysis (STA) technique including a main process and a parallel process is described. In the main process, an IC design can be loaded and then linked to a cell library. Timing constraints to be applied to the IC design can be loaded. A timing update for the IC design can be performed. A report based on the timing update can be output. In the parallel process, the interconnect parasitics can be back-annotated onto the IC design. In one embodiment, the interconnect parasitics can be processed and stored on disk. Information on attaching to the stored parasitic data can be generated and provided to the main process during the step of performing the timing update. The parallel process can run concurrently and asynchronously with the main process.

Parallel parasitic processing in static timing analysis

The method of mesh generation comprises a two-step automatic process that requires no user input once a geometric representation of the object has been provided to the apparatus. In the method, the object geometry is first defined in terms of object (subdomain) points, wherein each subdomain is a separate geometric region of the object such as a printed circuit board, a hole in the board, and a component mounted on the board. Bounding points defining a frame around the object geometry are then generated for producing a mesh consisting of at least one element. From the object points and the bounding points an initial mesh of elements is automatically generated according to a unique algorithm. In the second step of the process, each element in this mesh is then individually examined to determine if it meets a predetermined standard of acceptability and, if not, is refined. This process step employs a rule-based expert system to add additional points to the mesh at automatically determined locations for further mesh generation according to the unique algorithm employed. The steps of refinement repeat until each element in the mesh meets the acceptability standard or is considered no longer refinable.

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Beaverton, OR, United States of America

Patrick D Fortner