Parth Manishbhai Dodiya

Title: Parth Manishbhai Dodiya: Innovator in Delay-Line Architecture.

Introduction

Parth Manishbhai Dodiya is an inventor based in Bengaluru, India. His work includes a patent for a glitch-free delay-line architecture, and he is associated with Cadence Design Systems, Inc.

Latest Patents

Dodiya’s patent, “Glitch-Free Delay Line Architecture—Dynamically Updating a Delay Line Code,” describes a circuit designed to update a delay-line code. It uses two chains of interleaved logic gates to generate separate clock paths. Before a code update, the output of at least one logic gate is forced to zero, helping prevent glitches during the update. Dodiya is credited with 1 patent.

Career Highlights

Dodiya’s patented work addresses the challenge of updating delay-line codes while maintaining stable circuit behavior. His professional association with Cadence Design Systems, Inc. places this work within the field of electronic design and semiconductor technology.

Collaborations

Dodiya’s listed coworkers include Jitendra Kumar Yadav and Sachin Ramesh Gugwad.

Conclusion

Parth Manishbhai Dodiya’s patent presents a circuit approach for dynamically updating delay-line codes while reducing the risk of glitches.