The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 26, 2026
Filed:
Jun. 07, 2024
Cadence Design Systems, Inc., San Jose, CA (US);
Parth Manishbhai Dodiya, Bangalore, IN;
Jitendra Kumar Yadav, Bengaluru Karnataka, IN;
Sachin Ramesh Gugwad, San Jose, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Dynamically updating a delay line code. A circuit for updating a delay line code is provided having a delay line having a first chain of interleaved logic gates and a second chain of interleaved logic gates. The circuit further include a first clock path generated based upon the first chain of interleaved logic gates and a second clock path generated based upon the second chain of interleaved logic gates, wherein an output of at least one logic gate is forced to zero prior to performing a code update.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile