Taoyuan, Taiwan

Pang-Chun Liu

This inventor holds 1 USPTO granted patent. Top assignees: National Taiwan University, Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pang-Chun Liu. Retrieved from https://idiyas.com/inventor/pang-chun-liu-7p3jdfed

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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% Patents Active = 100.0

Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2024

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1 patent (USPTO):Explore Patents

Title: Inventor Bio of Pang-Chun Liu

Introduction

Pang-Chun Liu is a notable inventor based in Taoyuan, Taiwan. He has made significant contributions to the field of memory devices, holding a patent that showcases his innovative approach to technology.

Latest Patents

His most recent patent is titled "Memory device and forming method thereof." This invention involves a memory device that comprises a source region, a drain region, a channel region, a gate dielectric layer, an MTJ stack, and a metal gate. The design features a unique arrangement of ferromagnetic layers and a tunnel barrier layer, enhancing the functionality of memory devices.

Career Highlights

Pang-Chun Liu has worked with prominent organizations, including Taiwan Semiconductor Manufacturing Company Ltd. and National Taiwan University. His experience in these institutions has allowed him to develop and refine his expertise in semiconductor technology and memory devices.

Collaborations

Throughout his career, Liu has collaborated with esteemed colleagues such as Ya-Jui Tsou and Wei-Jen Chen. These partnerships have contributed to the advancement of research and development in the field of memory technology.

Conclusion

Pang-Chun Liu's innovative work in memory devices and his collaborations with leading professionals in the industry highlight his significant impact on technology. His contributions continue to influence advancements in semiconductor design and memory solutions.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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