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For the Inventor, By the Inventor

Osaka, Japan

Nobufusa Iwanishi

This inventor holds 15 USPTO granted patents and 2 published patent applications. Top assignees: Matsushita Electric Industrial Co., Ltd., Panasonic Corporation, Other. Active years: 1998-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Nobufusa Iwanishi. Retrieved from https://idiyas.com/inventor/nobufusa-iwanishi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 15 

% Patents Active = 53.3

Average Co-Inventor Count = 2.2

ph-index = 9

Forward Citations = 163(Granted Patents)


Location History:

  • Osaka, JP (1998 - 2010)
  • Hirakata, JP (2005 - 2011)

Company Filing History:

goldMedal12 out of 27,375 
 
Matsushita Electric Industrial Co., Ltd.
 patents
silverMedal2 out of 16,454 
 
Panasonic Corporation
 patents
bronzeMedal1 out of 834,570 
Other
 patents

Years Active: 1998-2011

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15 patents (USPTO):Explore Patents
1. 7925998 - Delay calculating method in semiconductor integrated circuit (2011-04-12),
2. 7831949 - Method of designing semiconductor integrated circuit, designing apparatus, semiconductor integrated circuit system, semiconductor integrated circuit mounting substrate, package and semiconductor integrated circuit (2010-11-09),
3. 7225418 - Operation analyzing method for semiconductor integrated circuit device, analyzing system used in the same, and optimization design method using the same (2007-05-29),
4. 7107557 - Method for calculation of cell delay time and method for layout optimization of semiconductor integrated circuit (2006-09-12),
5. 6988254 - Method for designing semiconductor integrated circuit (2006-01-17),
6. 6938233 - Method and apparatus for designing semiconductor integrated circuit device based on voltage drop distribution (2005-08-30),
7. 6795802 - Apparatus and method for calculating temporal deterioration margin amount of LSI, and LSI inspection method (2004-09-21),
8. 6718529 - Method for calculation of cell delay time (2004-04-06),
9. 6629299 - Delay library representation method, delay library generation method and delay calculation method using the delay library (2003-09-30),
10. 6498515 - Semiconductor integrated circuit and method for designing the same (2002-12-24),
11. 6396307 - Semiconductor integrated circuit and method for designing the same (2002-05-28),
12. 6278964 - Hot carrier effect simulation for integrated circuits (2001-08-21),
13. 6047247 - Method of estimating degradation with consideration of hot carrier (2000-04-04),
14. 6038397 - System for allocating the memory area of second data which value need (2000-03-14),
15. 5761081 - Method of evaluating signal propagation delay in logic integrated circuit (1998-06-02),

Title: Nobufusa Iwanishi: Innovator in Semiconductor Technology

Introduction

Nobufusa Iwanishi is a prominent inventor based in Osaka, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 15 patents. His work has focused on improving the design and functionality of semiconductor integrated circuits.

Latest Patents

One of Iwanishi's latest patents is a delay calculating method in semiconductor integrated circuits. This method involves obtaining an input pin capacitance of a cell in advance through a function expression. The delay is calculated by considering the input pin capacitance as a function of input slew and drive load capacitance. Additionally, in a cell characterizing process, the total volume of current running into an input terminal is measured before the voltage reaches a reference level, allowing for a more accurate approximation of the real input pin capacitance. Another notable patent involves a method of designing semiconductor integrated circuits, which enhances workability as the scale of large-scale integration (LSI) increases. This method includes a reverse design flow, where the mounting substrate is designed first, followed by the package substrate and the layout design of the LSI.

Career Highlights

Throughout his career, Nobufusa Iwanishi has worked with notable companies such as Matsushita Electric Industrial Co., Ltd. and Panasonic Corporation. His experience in these organizations has allowed him to develop innovative solutions in semiconductor design and technology.

Collaborations

Iwanishi has collaborated with several talented individuals in his field, including Yoshiyuki Kawakami and Noriko Ishibashi. These collaborations have contributed to the advancement of semiconductor technologies and the successful implementation of his patented methods.

Conclusion

Nobufusa Iwanishi's contributions to semiconductor technology through his innovative patents and collaborations have significantly impacted the industry. His work continues to influence the design and functionality of integrated circuits, showcasing the importance of innovation in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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