The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 09, 2010
Filed:
Jun. 28, 2007
Shinya Tokunaga, Kyoto, JP;
Mitsumi Ito, Kyoto, JP;
Nobufusa Iwanishi, Osaka, JP;
Koichi Seko, Osaka, JP;
Hiroaki Suzuki, Hyogo, JP;
Hiroyuki Tanaka, Kyoto, JP;
Yuichi Nishimura, Hyogo, JP;
Kazuhiko Fujimoto, Osaka, JP;
Shinya Tokunaga, Kyoto, JP;
Mitsumi Ito, Kyoto, JP;
Nobufusa Iwanishi, Osaka, JP;
Koichi Seko, Osaka, JP;
Hiroaki Suzuki, Hyogo, JP;
Hiroyuki Tanaka, Kyoto, JP;
Yuichi Nishimura, Hyogo, JP;
Kazuhiko Fujimoto, Osaka, JP;
Panasonic Corporation, Osaka, JP;
Abstract
To provide a method of designing a semiconductor integrated circuit with a high workability also in an increase in a scale of an LSI and an enhancement in an integration and designing a semiconductor integrated circuit system in which an unnecessary radiation is reduced and which is excellent in a heat characteristic, a reverse design flow to that in the conventional art is implemented, and a mounting substrate such as a printed-circuit board is first designed and a package substrate for mounting an LSI is designed based on a result of the design of the mounting substrate, and a layout design of the LSI to be mounted on the package substrate is then carried out.