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Sunnyvale, CA, United States of America

Nishath Verghese

USPTO Granted Patents = 5

Average Co-Inventor Count = 2.7

ph-index = 5

Forward Citations = 261(Granted Patents)

Location History:

Sunnyvale, CA (US) (2007 - 2010)
Santa Clara, CA (US) (2010 - 2012)

Company Filing History:

Cadence Design Systems, Inc.

Years Active: 2007-2012

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5 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8225248 - Timing, noise, and power analysis of integrated circuits (2012-07-17),

2. 7844438 - Method to analyze and correct dynamic power grid variations in ICs (2010-11-30),

3. 7673260 - Modeling device variations in integrated circuit design (2010-03-02),

4. 7359843 - Robust calculation of crosstalk delay change in integrated circuit design (2008-04-15),

5. 7310792 - Method and system for modeling variation of circuit parameters in delay calculation for timing analysis (2007-12-18),

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