Navneet Mohindru

Title: Innovations by Navneet Mohindru

Introduction

Navneet Mohindru is a prominent inventor based in San Jose, California. He has made significant contributions to the field of integrated circuit design through his innovative patent. His work focuses on improving the efficiency of routing congestion analysis in electronic designs.

Latest Patents

Navneet holds a patent titled "Efficient apparatus and method for analysis of RTL structures that cause physical congestion." This invention features a logical congestion metric analysis engine that predicts pre-placement routing congestion of integrated circuit designs. The engine employs new congestion-predicting metrics derived from structural register transfer level (RTL). It compares multiple metrics to those stored in a knowledge base to predict routing congestion. The knowledge base contains routing results for multiple designs using the same technology. For each design, the knowledge base holds pre-placement metric values and the corresponding post-placement and routing congestion results. Additionally, a logical congestion debug tool allows users to visualize and fix congestion issues.

Career Highlights

Navneet has been instrumental in advancing the field of electronic design automation. His work at Atrenta, Inc. has positioned him as a key player in developing tools that enhance the design process for integrated circuits. His innovative approach has led to improved methodologies that benefit engineers and designers alike.

Collaborations

Navneet has collaborated with notable colleagues such as Ravi Varadrajan and Jitendra Kumar Gupta. Their combined expertise has contributed to the success of various projects within the company.

Conclusion

Navneet Mohindru's contributions to the field of integrated circuit design through his innovative patent demonstrate his commitment to advancing technology. His work continues to influence the industry and improve design methodologies.