The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2014
Filed:
Jul. 26, 2013
Atrenta, Inc., San Jose, CA (US);
Ravi Varadrajan, Fremont, CA (US);
Jitendra Gupta, Pleasanton, CA (US);
Priyank Mittal, Ghaziabad, IN;
Tapeesh Gupta, Delhi, IN;
Navneet Mohindru, San Jose, CA (US);
Atrenta, Inc., San Jose, CA (US);
Abstract
A logical congestion metric analysis engine predicts pre-placement routing congestion of integrated circuit designs. The engine uses a method employing new congestion-predicting metrics derived from structural register transfer level (RTL). The method compares multiple metrics to those stored in a knowledge base to predict routing congestion. The knowledge base contains routing results for multiple designs using the same technology. For each design the knowledge base holds pre-placement metric values and the corresponding post-placement and routing congestion results. A logical congestion debug tool allows users to visualize and fix congestion issues.