This inventor holds 1 USPTO granted patent. Top assignee: Achronix Semiconductor Corporation. Active years: 2026.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2026
Title: Innovator Naveen Bharathwaj Akesh: Pioneering FPGA Memory Solutions
Introduction
Naveen Bharathwaj Akesh is an accomplished inventor based in Los Gatos, California. He has made significant contributions to the field of memory technology, particularly through his innovative patent related to FPGA memory systems. His work is characterized by a focus on efficiency and resource optimization in memory design.
Latest Patents
Naveen holds a patent for an "FPGA memory with auto address mode." This invention addresses the common issue of memory blocks consuming excessive switch box resources. The patented technology allows for an 8-bit memory system that utilizes multiplexed address and data lines, significantly reducing the number of required address lines. By providing an initial address and a stride before the writing process, the memory block can automatically determine the next address for writing, enhancing efficiency and reducing the need for additional address signals.
Career Highlights
Naveen is currently employed at Achronix Semiconductor Corporation, where he continues to develop cutting-edge memory solutions. His expertise in FPGA technology has positioned him as a valuable asset to the company. His innovative approach to memory design has garnered attention within the industry, showcasing his ability to solve complex engineering challenges.
Collaborations
Naveen collaborates with talented professionals in his field, including his coworker Raymond Nijssen. Together, they work on advancing memory technologies and exploring new applications for their inventions.
Conclusion
Naveen Bharathwaj Akesh is a notable inventor whose work in FPGA memory technology exemplifies innovation and efficiency. His contributions to the field are paving the way for future advancements in memory design.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile