Narendra B Devta-Prasanna

Title: Innovations by Narendra B Devta-Prasanna

Introduction

Narendra B Devta-Prasanna is a notable inventor based in Milpitas, CA (US). He has made significant contributions to the field of integrated circuits (IC) through his innovative patents. With a total of 3 patents, his work focuses on enhancing the evaluation and testing of small delay defects in ICs.

Latest Patents

One of his latest patents is titled "Method and an apparatus for evaluating small delay defect coverage of a test pattern set on an IC." This invention discloses a method that includes selecting a transition fault detected by a test pattern set, identifying path delays of the longest testable and tested paths, and calculating the small delay defect coverage (SDDC) for the transition fault. Another significant patent is the "Method for generating test patterns for small delay defects." This method involves generating a traditional delay fault pattern, fault grading it for small delay defect coverage, and producing timing-aware delay fault patterns for timing-aware target faults.

Career Highlights

Narendra is currently employed at LSI Corporation, where he applies his expertise in integrated circuit design and testing. His innovative approaches have contributed to advancements in the reliability and performance of ICs.

Collaborations

He has collaborated with notable colleagues such as Sandeep Kumar Goel and Ritesh P Turakhia, further enhancing the impact of his work in the field.

Conclusion

Narendra B Devta-Prasanna's contributions to the field of integrated circuits through his patents demonstrate his commitment to innovation and excellence. His work continues to influence the development of reliable testing methods for ICs.