The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 20, 2013

Filed:

Apr. 09, 2009
Applicants:

Narendra B. Devta-prasanna, Milpitas, CA (US);

Sandeep Kumar Goel, Milpitas, CA (US);

Inventors:

Narendra B. Devta-Prasanna, Milpitas, CA (US);

Sandeep Kumar Goel, Milpitas, CA (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3181 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and an apparatus for evaluating SDDC of a test pattern set are disclosed. In one embodiment, the method includes: (1) selecting a transition fault of an IC detected by a test pattern set, the transition fault occurring at a fault site of the IC, (2) identifying path delays of a longest testable path and a longest tested path of the IC, wherein both the longest testable path and the longest tested path include the fault site, (3) determining a SDD detection probability for both the longest testable path and the longest tested path based on a probability that a SDD will be detected if present at the fault site and (4) calculating SDDC for the transition fault by dividing the SDD detection probability of the longest tested path by the SDD detection probability of the longest testable path.


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