Naga Gollakota

Title: Naga Gollakota and His Patent in Semiconductor Testing.

Introduction

Naga Gollakota is an inventor associated with Folsom, California, and Intel Corporation. His patent work addresses a method for applying weighted random patterns in partial-scan testing.

Latest Patents

The provided information lists one patent for Gollakota: “Method for Application of Weighted Random Patterns to Partial Scan.” The invention describes generating deterministic patterns for a partial-scan design and grouping patterns according to the number of capture clocks between adjacent scan loads. A computer determines weights for each group, which a tester uses to filter weighted random test patterns. The tester then applies the filtered patterns and the corresponding capture-clock pulses to the device under test. Gollakota is credited with 1 patent.

Career Highlights

Gollakota is associated with Intel Corporation. His listed patent focuses on a testing approach that combines deterministic pattern information with weighted random testing for partial-scan designs.

Collaborations

The provided information names David M. Wu and Praveen K. Parvathala as Gollakota’s coworkers. It does not specify their roles in the patent or describe particular collaborative projects.

Conclusion

Naga Gollakota’s listed patent presents a structured way to apply weighted random patterns in partial-scan testing, reflecting his connection to semiconductor test innovation at Intel Corporation.