Mitch Liu

Title: Mitch Liu - Innovator in Flash Memory Technology

Introduction

Mitch Liu is a prominent inventor based in Santa Clara, CA. He has made significant contributions to the field of flash memory technology, holding a total of 5 patents. His work focuses on enhancing the efficiency and functionality of memory devices.

Latest Patents

One of Mitch Liu's latest patents is titled "Multiple erase block tagging in a flash memory device." This innovation allows for the parallel tagging of multiple memory devices by issuing an erase pulse to those that do not have memory blocks with erase block latches indicating that the block is erased. The status of the memory block is read after the erase pulse, and if there are blocks remaining to be erased, unique erase block tag patterns are generated for each memory block at a particular sector address. These patterns are transmitted in parallel to the memory devices in a data burst.

Another notable patent is "Integrated circuit design using charge pump modeling." This patent presents circuit models for simulating charge pumps, which facilitate the design of integrated circuits containing charge pumps. The models enable accurate simulation of actual charge pump behavior without the need for rigorous simulation of the multiple capacitive stages and the dedicated oscillator clocking the charge pump. The various embodiments utilize a charge pump model with multiple pull-up stages, optimizing output current based on output voltage.

Career Highlights

Mitch Liu is currently employed at Micron Technology Incorporated, where he continues to innovate in the field of memory technology. His work has significantly impacted the design and functionality of integrated circuits.

Collaborations

Mitch collaborates with Scott N Gatzemeier, contributing to advancements in their shared field of expertise.

Conclusion

Mitch Liu's contributions to flash memory technology and integrated circuit design demonstrate his commitment to innovation and excellence. His patents reflect a deep understanding of memory devices and their operational efficiencies.