Micron Technology Incorporated

Mitch Liu

Scott N Gatzemeier

A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is erased. The status of the memory block is read after the erase pulse. If there are blocks remaining to be erased, erase block tag patterns are generated. Each memory block at a particular sector address has a unique erase block tag pattern to set the erase block latch for that particular memory block. The patterns are transmitted in parallel to the memory devices in a data burst.

Multiple erase block tagging in a flash memory device

Circuit models for the simulation of charge pumps facilitate design of integrated circuits containing charge pumps. Such models facilitate accurate simulation of actual charge pump behavior without the need to rigorously simulate the multiple capacitive stages of an actual charge pump and the dedicated oscillator clocking the charge pump. The various embodiments utilize a charge pump model having multiple pull-up stages. At lower output voltages, the pull-up stages each provide an output current. These output currents are added together as the output current of the charge pump. Each pull-up stage automatically shuts off when the output voltage approaches a dedicated voltage source for that pull-up stage. As the output voltage increases, less current is output due to the deactivation of pull-up stages.

Integrated circuit design using charge pump modeling

A master block lock control word is written to a mini array of non-volatile fuses. The control word is recalled and decoded. A successful recall of the control word generates an indication that the master block lock bit is permanently disabled from subsequent changes.

Growing community of inventors

Santa Clara, CA, United States of America

Mitch Liu