Kaohsiung, Taiwan

Min-Yu Chen

This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Min-Yu Chen. Retrieved from https://idiyas.com/inventor/min-yu-chen-opvlqxij

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0

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Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Min-Yu Chen and Advances in Semiconductor Interposer Design

Introduction

Min-Yu Chen is an inventor associated with Taiwan Semiconductor Manufacturing Company Limited and based in Kaohsiung, Taiwan. His patent work addresses interposer design for advanced semiconductor packaging, with a focus on resisting deformation.

Latest Patents

Chen is named on 1 patent: “Deformation-resistant interposer for a local silicon interconnect and methods for forming the same.” The invention describes a composite interposer combining a local-silicon-interconnect-containing interposer, which includes a local silicon interconnect bridge, with an organic interposer above it. The organic interposer contains redistribution dielectric layers embedding wiring interconnects, as well as a metallic counter-deformation structure. That structure uses multiple metallic vias positioned between two vertically spaced metallic plates, one on each side of the vias. The design is intended to help resist deformation in the interposer assembly.

Career Highlights

Chen’s listed patent reflects work on semiconductor packaging structures that integrate silicon interconnects with organic redistribution layers. The disclosed counter-deformation structure brings together metallic vias and plates to address mechanical stability in a complex interposer.

Collaborations

Chen’s listed coworker is PO-Chen Lai. Their association is reflected in the patent information provided.

Conclusion

Min-Yu Chen’s patent focuses on a deformation-resistant interposer architecture that combines local silicon interconnect technology with an organic interposer and a metallic reinforcement structure.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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