For the Inventor, By the Inventor

Enter inventor name

Cupertino, CA, United States of America

Min Chie Jeng

This inventor holds 4 USPTO granted patents. Top assignee: Semiconductor Manufacturing International (Shanghai) Corporation. Active years: 2010-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Min Chie Jeng. Retrieved from https://idiyas.com/inventor/min-chie-jeng-4k1x32sk

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 4

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 2

Forward Citations = 6(Granted Patents)

Location History:

Keelung, CN (2010)
Keelung, TW (2012)
Cupertino, CA (US) (2012 - 2014)

Company Filing History:

Semiconductor Manufacturing International (Shanghai) Corporation

Years Active: 2010-2014

Loading Chart...

4 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8686507 - System and method for I/O ESD protection with floating and/or biased polysilicon regions (2014-04-01),

2. 8319286 - System and method for input pin ESD protection with floating and/or biased polysilicon regions (2012-11-27),

3. 8283726 - System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors (2012-10-09),

4. 7642602 - System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors (2010-01-05),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

Loading…