System and method for i/o esd protection with polysilicon regions fabricated by processes for making core transistors

Abstract

A system and method for electrostatic discharge protection. The system includes a first transistor coupled to a first system and including a first gate, a first dielectric layer located between the first gate and a first substrate, a first source, and a first drain. The first system includes or is coupled to a core transistor, and the core transistor includes a second gate, a second dielectric layer located between the second gate and a second substrate, a second source, and a second drain. The first transistor is selected from a plurality of transistors, and the plurality of transistors include a plurality of gate regions, a plurality of source regions, and a plurality of drain regions. A plurality of polysilicon regions are disposed in an proximity of at least one of the plurality of gate regions. The plurality of polysilicon regions are separated from the first substrate a plurality of dielectric layers.