Edmonds, WA, United States of America

Michael Scott Meredith

This inventor holds 1 USPTO granted patent. Top assignee: Cadence Design Systems, Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Michael Scott Meredith. Retrieved from https://idiyas.com/inventor/michael-scott-meredith-mjj9oxkp

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Michael Scott Meredith and Power-Aware High-Level Synthesis

Introduction

Michael Scott Meredith is an inventor based in Edmonds, Washington, whose patent work addresses power management in digital circuit design. His disclosed invention concerns integrating power shut-off capabilities into a high-level synthesis flow.

Latest Patents

Meredith is associated with 1 patent, titled “Power shut-off in high-level synthesis flow.” The patent describes methods and systems that process a high-level synthesis (HLS) file to identify a circuit-design portion designated for power shut-off. The HLS file is then synthesized into a register-transfer-level (RTL) design in which logic elements implementing that portion can be shut down. The process also generates a Power Intent File that communicates retention and non-retention registers to downstream electronic design automation tools.

Career Highlights

Meredith works at Cadence Design Systems, Inc., a company whose work includes tools and technologies for electronic design and semiconductor development. His patent reflects an approach to carrying power-management intent from an HLS description into RTL and subsequent design stages.

Collaborations

Stephen B. Sutherland and Felice Balarin are identified as Meredith’s coworkers. The patent’s described workflow connects high-level design specifications with RTL implementation and downstream design tools.

Conclusion

Michael Scott Meredith’s patent focuses on enabling power shut-off during high-level synthesis while preserving information needed by later design stages. It illustrates how power-management requirements can be incorporated into the circuit-design workflow.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…