The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2026
Filed:
Apr. 03, 2023
Cadence Design Systems, Inc., San Jose, CA (US);
Stephen B. Sutherland, Redmond, WA (US);
Felice Balarin, Berkeley, CA (US);
Sean Dart, Sammamish, WA (US);
Michael Scott Meredith, Edmonds, WA (US);
Mark A. Jensen, Pittsburgh, PA (US);
Jeffrey Mark Marshall, Raleigh, NC (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Methods and systems are provided for performing power shut-off in a high-level synthesis flow. The methods and systems access a high level synthesis flow (HLS) file representing a circuit design. The methods and systems process the HLS file to identify a portion of the circuit design that is associated with power shut-off indicating that the portion of the circuit design is enabled for shut down. The methods and systems, based on identifying the portion of the circuit design that is associated with power shut-off, synthesize the HLS file into a register-transfer level (RTL) design of the circuit design in which one or more logic elements that implement the portion of the circuit design are enabled for shut down. In addition to the generation of the RTL design, a Power Intent File is generated to communicate a list of retention and non-retention registers to the downstream EDA flow.