Boise, ID, United States of America

Michael G Miller

This inventor holds 63 USPTO granted patents and 22 published patent applications and 2 EPO patents, primarily in Memory Management (CPC class G11C). Top assignees: Micron Technology Incorporated, Other. Active years: 1994-2026.

USPTO Granted Patents = 63 

% Patents Active = 100.0

 

Average Co-Inventor Count = 4.5

ph-index = 6

Forward Citations = 226(Granted Patents)

Forward Citations (Not Self Cited) = 187(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Miami Beach, FL (US) (1994)
  • Vancouver, WA (US) (2009 - 2014)
  • Boise, ID (US) (2018 - 2024)

Company Filing History:

goldMedal59 out of 39,125 
 
Micron Technology Incorporated
 patents
silverMedal2 out of 834,350 
Other
 patents
where one patent can have more than one assignee

Years Active: 1994-2026

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Areas of Expertise:
Error Handling
Memory Devices
Dynamic Caches
Static Caches
Adaptive Error Avoidance
Asynchronous Power Loss
Garbage Collection
Workload Adaptive Scans
Voltage Adjustment
Diagonal Page Mapping
Read Disturb Mitigation
Calibration Error Recovery
63 patents (USPTO):Explore Patents

Title: Michael G Miller: A Technological Innovator in Memory Devices

Introduction:

Meet Michael G Miller, a brilliant inventor hailing from Boise, ID (US). With an impressive count of 49 patents, he has significantly contributed to the field of memory devices, particularly in the areas of mixed mode block operation and power loss handling. As an engineer at Micron Technology Incorporated, Michael has made substantial advancements in the industry. Let's delve into his latest patents, career highlights, and collaborations, highlighting his invaluable contributions.

Latest Patents:

Michael G Miller's recent patents showcase his expertise and innovative thinking. One of his notable inventions is the "Operation of Mixed Mode Blocks" – a groundbreaking apparatus and method for operating mixed mode blocks in memory devices. This patent outlines a technique to track and adjust cycle counts differently for single level cell (SLC) mode and extra level cell (XLC) mode operations on mixed mode blocks.

Another remarkable patent is the "Selective Dummy Writes for Asynchronous Power Loss Handling in Memory Devices." This invention addresses the need for efficient power loss handling in memory devices by performing dummy write operations on specific pages based on programmed zeros. By considering threshold constraints, the memory device can intelligently determine whether to execute a dummy write operation on the last written page.

Career Highlights:

Throughout his career, Michael G Miller has been an invaluable asset to Micron Technology Incorporated. His expertise and relentless pursuit of innovation have led to numerous advancements in memory device technologies. Through his patents, Michael has demonstrated his deep understanding of mixed mode block operations and intelligent power loss handling, pushing the boundaries of what is possible in this field.

Collaborations:

Michael G Miller has had the privilege of collaborating with talented individuals who share his passion for innovation. Two notable colleagues in his network are Kishore Kumar Muchherla and Renato C Padilla, both celebrated professionals in the field. Through collaboration and teamwork, Michael has been able to leverage diverse skill sets and perspectives, further promoting cutting-edge research and development.

Conclusion:

Michael G Miller's contributions to the field of memory devices, as exemplified by his numerous patents, highlight his prowess as a technological innovator. From advancing mixed mode block operations to optimizing power loss handling, his expertise has played a crucial role in shaping the industry. With a remarkable career at Micron Technology Incorporated and notable collaborations, Michael G Miller continues to excel as a trailblazer within the realm of memory device technology.

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