The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 29, 2024

Filed:

Dec. 03, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kishore K. Muchherla, Fremont, CA (US);

Ashutosh Malshe, Fremont, CA (US);

Sampath K. Ratnam, Boise, ID (US);

Peter Feeley, Boise, ID (US);

Michael G. Miller, Boise, ID (US);

Christopher S. Hale, Boise, ID (US);

Renato C. Padilla, Folsom, VA (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 11/34 (2006.01); G06F 12/02 (2006.01); G06F 12/0888 (2016.01); G06F 12/0893 (2016.01);
U.S. Cl.
CPC ...
G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G06F 11/34 (2013.01); G06F 11/348 (2013.01); G06F 12/0246 (2013.01); G06F 12/0888 (2013.01); G06F 12/0893 (2013.01); G06F 2201/885 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/222 (2013.01); G06F 2212/502 (2013.01); G06F 2212/601 (2013.01); G06F 2212/7205 (2013.01); G06F 2212/7206 (2013.01);
Abstract

Memory devices are disclosed. A memory device may include dynamic cache, static cache, and a memory controller. The memory controller may be configured to disable the static cache responsive to a number of program/erase (PE) cycles consumed by the static cache being greater than an endurance of the static cache. The memory controller may also be configured to disable the dynamic cache responsive to a number of PE cycles consumed by the dynamic cache being greater than an endurance of the dynamic cache. Associated methods and systems are also disclosed.


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