North Plains, OR, United States of America

MD Masud Parvez Arnob

This inventor holds 1 USPTO granted patent. Top assignee: Intel Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: MD Masud Parvez Arnob. Retrieved from https://idiyas.com/inventor/md-masud-parvez-arnob

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: MD Masud Parvez Arnob and Semiconductor Innovation.

Introduction

MD Masud Parvez Arnob is an inventor associated with Intel Corporation and based in North Plains, Oregon. His patent work addresses semiconductor device design and fabrication.

Latest Patents

Arnob is associated with 1 patent, titled “Amorphized Subfins Using Backside Implantation.” The patent describes techniques for forming semiconductor devices with subfins that are at least partially amorphized. A backside ion implantation process can introduce dopants, such as germanium, into a subfin to create an amorphized portion.

In an example device, a gate structure is formed around or on a semiconductor region made from a fin. The fin includes a subfin next to a dielectric fill. The amorphized portion may lie beneath the gate and between the source and drain regions. Depending on the implementation, it can extend from the subfin’s bottom surface to just below the gate structure while leaving some crystalline material beneath the gate.

Career Highlights

Arnob’s listed patent reflects work on semiconductor processing methods that use backside implantation to modify subfin material. The described approach focuses on controlling the subfin’s structure within a transistor device.

Collaborations

Arnob’s listed coworkers include Adam Neale and Soonyoung Lee. The patent is associated with Intel Corporation.

Conclusion

MD Masud Parvez Arnob’s patent describes a backside implantation technique for creating amorphized portions in semiconductor subfins, contributing to ongoing innovation in semiconductor device fabrication.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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