The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2026
Filed:
Jun. 30, 2023
Intel Corporation, Santa Clara, CA (US);
Adam Neale, Portand, OR (US);
Soonyoung Lee, Portland, OR (US);
MD Masud Parvez Arnob, North Plains, OR (US);
Norbert Seifert, Beaverton, OR (US);
Jeffrey Hicks, Banks, OR (US);
Aurelia Chi Wang, Hillsboro, OR (US);
Giorgio Mariottini, Hillsboro, OR (US);
Jaladhi Mehta, Beaverton, OR (US);
Conor P. Puls, Portland, OR (US);
Anant H. Jahagirdar, Portland, OR (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
Techniques to form semiconductor devices that include subfins that are at least partially amorphized are described. A backside dopant implantation process using dopants (e.g., germanium) may be used to create amorphous semiconductor material in the subfins. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region formed from a fin of semiconductor material. The fin includes a subfin laterally adjacent to a dielectric fill. A backside ion implantation process may be used to implant dopants such as Ge into the subfin and consequently form an amorphized portion of the subfin. In some examples, the amorphized portion is under the gate structure and laterally between a source region and a drain region. The amorphized portion may extend from a bottom surface of the subfin to just under the gate structure, and in some cases, leave a crystalline portion of subfin below the gate structure.