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For the Inventor, By the Inventor

Austin, TX, United States of America

Matthew S Berzins

This inventor holds 33 USPTO granted patents, primarily in Low Power Circuit Design. Top assignees: Samsung Electronics Co., Ltd., Cypress Semiconductor Corporation, Freescale Semiconductor,inc.. Active years: 2004-2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Matthew S Berzins. Retrieved from https://idiyas.com/inventor/matthew-s-berzins

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 33

% Patents Active = 72.7

Average Co-Inventor Count = 2.3

ph-index = 7

Forward Citations = 150(Granted Patents)


Location History:

  • Hwasung, KR (2016)
  • Hwaswung, KR (2018)
  • Austin, TX (US) (2004 - 2019)
  • Cedar Park, TX (US) (2007 - 2021)

Company Filing History:

goldMedal24 out of 132,108 
 
Samsung Electronics Co., Ltd.
 patents
silverMedal6 out of 3,596 
 
Cypress Semiconductor Corporation
 patents
bronzeMedal3 out of 5,491 
 
Freescale Semiconductor,inc.
 patents

Years Active: 2004-2021

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Areas of Expertise:
Power Consumption
Integrated Clock Gating
Flip-Flops
Voltage Operation
Standard Cell
Clock Mesh
High Speed
Differential Signal
CMOS Translation
Scan Chain Circuits
Power Gating
Jitter Immunity
33 patents (USPTO):Explore Patents
1. 11092649 - Method for reducing power consumption in scannable flip-flops without additional circuitry (2021-08-17),
2. 10819342 - Low-power low-setup integrated clock gating cell with complex enable selection (2020-10-27),
3. 10784864 - Low power integrated clock gating system and method (2020-09-22),
4. 10784198 - Power rail for standard cell block (2020-09-22),
5. 10748889 - Power grid and standard cell co-design structure and methods thereof (2020-08-18),
6. 10720204 - System and method for improving scan hold-time violation and low voltage operation in sequential circuit (2020-07-21),
7. 10607982 - Layout connection isolation technique for improving immunity to jitter and voltage drop in a standard cell (2020-03-31),
8. 10581410 - High speed domino-based flip flop (2020-03-03),
9. 10382017 - Dynamic flip flop having data independent P-stack feedback (2019-08-13),
10. 10353000 - Multi-bit flip-flops (2019-07-16),
11. 10298235 - Low power integrated clock gating cell using controlled inverted clock (2019-05-21),
12. 10262723 - System and method for improving scan hold-time violation and low voltage operation in sequential circuit (2019-04-16),
13. 9904758 - Using deep sub-micron stress effects and proximity effects to create a high performance standard cell (2018-02-27),
14. 9899990 - Semiconductor circuit including flip-flop (2018-02-20),
15. 9891283 - Multi-bit flip-flops and scan chain circuits (2018-02-13),

Title: The Innovative Contributions of Matthew S. Berzins in Power Consumption Technology

Introduction: Matthew S. Berzins, based in Austin, TX, is a prolific inventor with 33 patents to his name. His work primarily focuses on enhancing the efficiency of electronic circuits, especially in reducing power consumption. Berzins has significantly contributed to the field through innovative methodologies that facilitate improved performance and reduced energy usage.

Latest Patents: Among his latest innovations is a patent titled "Method for reducing power consumption in scannable flip-flops without additional circuitry." This invention involves a sophisticated apparatus designed to manage power signals effectively. It features a latching circuit powered by high and low voltage signals, enabling energy-efficient operations without the need for additional components.

Another noteworthy patent from Berzins is the "Low-power low-setup integrated clock gating cell with complex enable selection." This design incorporates a NOR gate, complex gate, and NAND gate, working together to output an inverted enabled clock signal. By utilizing these advanced components, Berzins has developed a clock gating cell that minimizes power consumption while maintaining operational integrity.

Career Highlights: Matthew S. Berzins has had a distinguished career, with significant tenure at reputable companies such as Samsung Electronics and Cypress Semiconductor Corporation. His work at these organizations has placed him at the forefront of innovation in semiconductor technology.

Collaborations: Throughout his career, Berzins has collaborated with notable colleagues, including Charles A. Cornell and Stephen Myles Prather. Together, they have tackled some of the most pressing challenges in the field, contributing to groundbreaking advancements in electronic design.

Conclusion: Matthew S. Berzins embodies the spirit of innovation through his extensive work in power consumption technology. With 33 patents reflecting his dedication and creativity, his contributions not only enhance electronic performance but also pave the way for a more energy-efficient future in technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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