The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 13, 2018

Filed:

Sep. 30, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Min-Su Kim, Hwaseong-si, KR;

Matthew Berzins, Hwaswung, KR;

Jong-Woo Kim, Osan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); H03K 19/21 (2006.01); H03K 3/037 (2006.01); G01R 31/3185 (2006.01); H03K 3/3562 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/31723 (2013.01); G01R 31/31727 (2013.01); G01R 31/318541 (2013.01); H03K 3/0372 (2013.01); H03K 3/35625 (2013.01); H03K 19/21 (2013.01);
Abstract

A multi-bit flip-flop includes a plurality of multi-bit flip-flop blocks that share a clock signal. Each of the multi-bit flip-flop blocks includes a single inverter and a plurality of flip-flops. The single inverter generates an inverted clock signal by inverting the clock signal. Each of the flip-flops includes a master latch part and a slave latch part and operates the master latch part and the slave latch part based on the clock signal and the inverted clock signal. Here, the flip-flops are triggered at rising edges of the clock signal. Thus, the multi-bit flip-flop operating as a master-slave flip-flop may minimize (or, reduce) power consumption occurring in a clock path through which the clock signal is transmitted.


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