Los Gatos, CA, United States of America

Matt F Vernon

This inventor holds 2 USPTO granted patents. Top assignee: Intel Corporation. Active years: 2007-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Matt F Vernon. Retrieved from https://idiyas.com/inventor/matt-f-vernon

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 2.0

ph-index = 2

Forward Citations = 5(Granted Patents)


Company Filing History:


Years Active: 2007-2010

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2 patents (USPTO):Explore Patents

Title: Matt F. Vernon and Semiconductor Mask Innovation.

Introduction

Matt F. Vernon is an inventor based in Los Gatos, California, and is associated with Intel Corporation. His patent work includes techniques for fabricating phase-shift masks used in semiconductor manufacturing. He is credited with 2 patents.

Latest Patents

Vernon’s listed patent, “Continuous Sloped Phase Edge Architecture Fabrication Technique Using Electron or Optical Beam Blur for Single Phase Shift Mask RET,” describes a phase-shift mask with continuous, sloped edges between phase-shift regions. The technique introduces a predetermined degree of defocus into the electron or optical beam used to image the mask pattern.

The sloped edges can help produce a “trimless” phase-shift mask, which does not require a separate binary trim mask and second exposure to remove phase conflicts. This approach addresses mask fabrication and patterning challenges in semiconductor lithography.

Career Highlights

Vernon’s listed invention focuses on improving phase-shift mask fabrication through controlled beam blur. The patent description connects this method to mask designs intended to simplify the exposure process.

Collaborations

Vernon’s listed coworker is Wen-Hao Cheng. Both are associated with the phase-shift mask invention described above.

Conclusion

Matt F. Vernon’s patent work highlights a mask-fabrication technique that uses controlled defocus to create continuous sloped phase edges and support trimless semiconductor patterning.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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