logo

For the Inventor, By the Inventor

Suwa, Japan

Masatoshi Tagaki

This inventor holds 16 USPTO granted patents and 1 published patent application. Top assignee: Seiko Epson Corporation. Active years: 2009-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Masatoshi Tagaki. Retrieved from https://idiyas.com/inventor/masatoshi-tagaki

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 16 

% Patents Active = 75.0

Average Co-Inventor Count = 2.0

ph-index = 4

Forward Citations = 41(Granted Patents)


Company Filing History:

goldMedal16 out of 34,238 
 
Seiko Epson Corporation
 patents

Years Active: 2009-2020

Loading Chart...
16 patents (USPTO):Explore Patents
1. 10658325 - Semiconductor device including a buffer layer structure for reducing stress (2020-05-19),
2. 10103120 - Semiconductor device including a buffer layer structure for reducing stress (2018-10-16),
3. 9842821 - Semiconductor device including semiconductor chip, wiring, conductive material, and contact part (2017-12-12),
4. 9515043 - Semiconductor device including a buffer layer structure for reducing stress (2016-12-06),
5. 9331039 - Semiconductor device including a buffer layer structure for reducing stress (2016-05-03),
6. 9093334 - Semiconductor device including a buffer layer structure for reducing stress (2015-07-28),
7. 8952554 - Semiconductor device including a buffer layer structure for reducing stress (2015-02-10),
8. 8878365 - Semiconductor device having a conductive layer reliably formed under an electrode pad (2014-11-04),
9. 8742601 - Semiconductor device including a buffer layer structure for reducing stress (2014-06-03),
10. 8614513 - Semiconductor device including a buffer layer structure for reducing stress (2013-12-24),
11. 8441125 - Semiconductor device (2013-05-14),
12. 7936064 - Semiconductor device (2011-05-03),
13. 7777334 - Semiconductor device having active element formation region provided under a bump pad (2010-08-17),
14. 7663180 - Semiconductor device (2010-02-16),
15. 7649260 - Semiconductor device (2010-01-19),

Title: Masatoshi Tagaki: Innovator in Semiconductor Technology

Introduction

Masatoshi Tagaki is a prominent inventor based in Suwa, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 16 patents. His work focuses on enhancing the performance and reliability of semiconductor devices.

Latest Patents

One of Masatoshi Tagaki's latest patents involves a semiconductor device that includes a buffer layer structure designed to reduce stress. This innovative device features a semiconductor chip with wiring that has a coupling part between sections of different widths. A pad is formed above the wiring, overlapping the coupling part, with a bump created on the pad. A buffer layer is strategically placed between the coupling part and the pad, covering the entire coupling area. Additionally, inorganic insulating layers are formed between the wiring and the buffer layer, as well as between the buffer layer and the pad. Notably, the buffer layer is made from a material other than resin and is softer than the inorganic insulating layer, which enhances the device's performance.

Career Highlights

Masatoshi Tagaki is currently employed at Seiko Epson Corporation, where he continues to innovate in the semiconductor field. His expertise and dedication have led to numerous advancements in semiconductor technology, making him a valuable asset to his company.

Collaborations

Throughout his career, Masatoshi has collaborated with talented individuals such as Takeshi Yuzawa and Akinori Shindo. These collaborations have fostered a creative environment that encourages innovation and the development of cutting-edge technologies.

Conclusion

Masatoshi Tagaki's contributions to semiconductor technology are noteworthy, and his patents reflect his commitment to innovation. His work continues to influence the industry, paving the way for future advancements in semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…