Chigasaki, Japan

Masanobu Shirakawa

This inventor holds 246 USPTO granted patents and 41 published patent applications and 1 EPO patent, primarily in Memory Systems (CPC class G11C16-0483). Top assignees: Kioxia Corporation, Toshiba Memory Corporation, Kabushiki Kaisha Toshiba. Active years: 2008-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Masanobu Shirakawa. Retrieved from https://idiyas.com/inventor/masanobu-shirakawa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 246 

% Patents Active = 95.1

 

Average Co-Inventor Count = 2.5

ph-index = 11

Forward Citations = 566(Granted Patents)

Forward Citations (Not Self Cited) = 394(Dec 10, 2025)


Inventors with similar research interests:

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Location History:

  • Fujisawa, JP (2008 - 2010)
  • San Jose, CA (US) (2013)
  • Chigasaki, Kanagawa, JP (2018)
  • Chigasaki, JP (2011 - 2024)
  • Chigasaki Kanagawa, JP (2015 - 2024)
  • Kanagawa, JP (2015 - 2024)

Company Filing History:


Years Active: 2008-2026

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Areas of Expertise:
Error Correction Code
Nonvolatile Memory
Semiconductor Device
Memory Controller
Data Reading
Erase Operation
Control Circuit
Memory Cell Arrays
Threshold Variation
Input/Output Buffer
Correction Value Table
Memory Device
246 patents (USPTO):Explore Patents

Title: Masanobu Shirakawa: Pioneering Innovator in the Memory Systems Domain

Introduction:

In the fast-paced world of technology, where memory systems play a crucial role, the name Masanobu Shirakawa stands out as a pioneering innovator. With an impressive portfolio of 195 patents, Shirakawa has made significant contributions to the field of memory systems and information processing. This article explores his latest patents, career highlights, collaborations, and the impact he has had on the industry.

Latest Patents:

Shirakawa's latest patents showcase his expertise and innovation in memory systems and information processing. One remarkable invention is the "Memory System and Information Processing System." This embodiment involves a memory system with a nonvolatile memory and a memory controller that executes a patrol process. This process includes reading data from the nonvolatile memory without outputting it to the host device. Additionally, another recent patent titled "Memory System" describes a memory system with a semiconductor memory and a controller. This invention employs word lines and memory cells to accomplish specific operations such as obtaining read voltages and reading data.

Career Highlights:

Throughout his accomplished career, Shirakawa has made notable contributions to the field. He has served in reputable companies, including Toshiba Memory Corporation (previously known as Toshiba Corporation). Working in such renowned organizations has provided him with valuable resources and opportunities to innovate. His collaborations with talented individuals have further amplified his impact on the industry.

Collaborations:

Shirakawa's success has been nurtured due to collaborations with esteemed colleagues. Among the notable individuals he has worked with are Marie Takada and Tsukasa Tokutomi. These fruitful collaborations have fostered an environment for knowledge exchange, idea generation, and the development of groundbreaking technologies in memory systems.

Conclusion:

Masanobu Shirakawa is a highly accomplished innovator in the domain of memory systems. With an extensive patent portfolio of 195 patents, his contributions have had a significant impact on the industry. His latest patents demonstrate his exceptional expertise in memory systems and information processing. Collaborating with esteemed colleagues, such as Marie Takada and Tsukasa Tokutomi, has further enhanced his contributions to the field. Masanobu Shirakawa's innovative spirit and commitment to pushing technological boundaries continue to shape the future of memory systems and beyond.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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