The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2026

Filed:

Aug. 06, 2024
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Marie Takada, Yokohama Kanagawa, JP;

Masanobu Shirakawa, Chigasaki Kanagawa, JP;

Naomi Takeda, Yokohama Kanagawa, JP;

Ryo Yamaki, Yokohama Kanagawa, JP;

Shogo Muto, Fujisawa Kanagawa, JP;

Hideki Yamada, Yokohama Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/349 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01);
Abstract

According to one embodiment, a memory system includes a memory chip and a memory controller. A first cell unit and a second cell unit are classified into a first group. A third cell unit is classified into a second group. The memory controller is configured to use a first correction amount of a read voltage when data of the first group is read and to use a second correction amount of the read voltage when data of the second group is read. When a time difference from a write operation of the first cell unit to the write operation of the second cell unit exceeds a reference value, the memory controller is configured to change a boundary position between the first group and the second group to between the first cell unit and the second cell unit, and to classify the second cell unit into the second group.


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