Karnataka, India

Manjunath Veerappa Chobari Patil

This inventor holds 2 USPTO granted patents and 5 published patent applications. Top assignee: Applied Materials, Inc.. Active years: 2025-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Manjunath Veerappa Chobari Patil. Retrieved from https://idiyas.com/inventor/manjunath-veerappa-chobari-patil

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 2 

% Patents Active = 100.0

Average Co-Inventor Count = 7.9

ph-index = 1


Company Filing History:


Years Active: 2025-2026

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2 patents (USPTO):Explore Patents

Title: Manjunath Veerappa Chobari Patil: Innovator in Semiconductor Processing

Introduction

Manjunath Veerappa Chobari Patil is a notable inventor based in Karnataka, India. He has made significant contributions to the field of semiconductor processing, particularly through his innovative patent.

Latest Patents

Manjunath holds a patent titled "Methods to eliminate deposition on wafer bevel and backside." This patent describes exemplary semiconductor processing chambers that include a chamber body defining a processing region. The chambers feature a substrate support with a recessed substrate seat and a shadow ring that extends around the peripheral edge of the substrate seat. Additionally, the design incorporates bevel purge openings and a gas flow path that enhances the efficiency of the semiconductor processing.

Career Highlights

Manjunath is currently employed at Applied Materials, Inc., a leading company in the semiconductor industry. His work focuses on improving semiconductor processing techniques, which are crucial for the advancement of technology in various electronic devices.

Collaborations

Some of his coworkers include Venkata Sharat Chandra Parimi and Zubin Huang, who contribute to the innovative environment at Applied Materials, Inc.

Conclusion

Manjunath Veerappa Chobari Patil is a distinguished inventor whose work in semiconductor processing has the potential to impact the industry significantly. His innovative approaches and collaborations with talented colleagues further enhance the advancements in this critical field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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