Mamoru Nishizaki

This inventor holds 13 USPTO granted patents and 3 published patent applications. Top assignee: Micron Technology Incorporated. Active years: 2015-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mamoru Nishizaki. Retrieved from https://idiyas.com/inventor/mamoru-nishizaki

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 13 (Patent Applications = 3)

% Patents Active = 84.6

Average Co-Inventor Count = 1.2

ph-index = 3

Forward Citations = 18(Granted Patents)

Location History:

Chuo-ku, JP (2015)
Kanagawa, JP (2022)
Yokohama, JP (2018 - 2024)

Company Filing History:

13 out of 39,176

Micron Technology Incorporated

patents

Years Active: 2015-2026

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13 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12755774 - Semiconductor device having row decoder circuit (2026-10-06),

2. 12676179 - Semiconductor device having row decoder circuit (2026-07-07),

3. 12094522 - Semiconductor device having read data buses and write data buses (2024-09-17),

4. 11984188 - Semiconductor device having sense amplifier (2024-05-14),

5. 11715522 - Semiconductor device equipped with column decoder circuit (2023-08-01),

6. 11495282 - Sense amplifier drivers, and related devices, systems, and methods (2022-11-08),

7. 10896718 - Multilayered network of power supply lines (2021-01-19),

8. 10580463 - Power supply wiring in a semiconductor memory device (2020-03-03),

9. 10468090 - Multilayered network of power supply lines (2019-11-05),

10. 10339980 - Apparatuses and methods for controlling wordlines and sense amplifiers (2019-07-02),

11. 10304497 - Power supply wiring in a semiconductor memory device (2019-05-28),

12. 10020038 - Apparatuses and methods for controlling wordlines and sense amplifiers (2018-07-10),

13. 9142629 - Semiconductor device having shared diffusion layer between transistors (2015-09-22),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

3 patents pending: