San Jose, CA, United States of America

Malay K Ganai

This inventor holds 2 USPTO granted patents and 1 published patent application. Top assignee: Synopsys, Inc.. Active years: 2017-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Malay K Ganai. Retrieved from https://idiyas.com/inventor/malay-k-ganai-c6qq72jz

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 2 

% Patents Active = 100.0

Average Co-Inventor Count = 1.8

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2017-2023

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2 patents (USPTO):Explore Patents

Title: Innovations by Malay K Ganai

Introduction

Malay K Ganai is an accomplished inventor based in San Jose, CA. He has made significant contributions to the field of functional verification through his innovative patents. With a total of 2 patents, his work focuses on enhancing the efficiency and accuracy of design verification processes.

Latest Patents

Ganai's latest patents include "Diversifying stimulus generation in constrained random simulation by learning distribution history." This patent describes techniques and systems for generating constrained random stimuli during functional verification of a design under verification (DUV). The embodiments can compute an observed probability distribution for each variable based on a first random solution generated using a set of constraints. Additionally, the system can compute a correction probability distribution for each variable based on the observed and intended probability distributions. This allows for the selection of random values for variables based on the correction probability distribution, continuously updating the observed probability distribution as constrained random stimuli are generated.

Another notable patent is the "System and method for netlist clock domain crossing verification." This system leverages RTL clock domain crossing (CDC) verification data and results. The netlist clock domain crossing verification system (NCDC) migrates RTL-level constraints and waivers to the netlist design, simplifying the verification process for users. The NCDC checks the netlist and generates a report comparing RTL-level CDC checking results to netlist-level results, making it easier to identify new issues.

Career Highlights

Malay K Ganai is currently employed at Synopsys, Inc., where he continues to innovate in the field of design verification. His work has been instrumental in advancing methodologies that improve the reliability of electronic designs.

Collaborations

Ganai collaborates with talented professionals in his field, including Mohamed Shaker Sarwary and Maher Mneimneh. These collaborations enhance the innovative capabilities of his projects and contribute to the overall success of their initiatives.

Conclusion

Malay K Ganai's contributions to the field of functional verification through his patents demonstrate his commitment to innovation and excellence. His work not only advances technology but also sets new standards in design verification processes.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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