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For the Inventor, By the Inventor

San Diego, CA, United States of America

Lun Bin Huang

This inventor holds 13 USPTO granted patents and 3 published patent applications and 1 EPO patent, primarily in Data Storage Optimization. Top assignees: Stmicroelectronics Gmbh, Hgst Technologies Santa Ana, Inc., S-Tec Corporation. Active years: 2004-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Lun Bin Huang. Retrieved from https://idiyas.com/inventor/lun-bin-huang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 13 

% Patents Active = 69.2


Average Co-Inventor Count = 2.4

ph-index = 5

Forward Citations = 77(Granted Patents)


Company Filing History:

goldMedal11 out of 2,891 
 
Stmicroelectronics Gmbh
 patents
silverMedal1 out of 23 
 
Hgst Technologies Santa Ana, Inc.
 patents
bronzeMedal1 out of 120 
 
S-Tec Corporation
 patents

Years Active: 2004-2016

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Areas of Expertise:
Max-Log-MAP
Viterbi Architecture
Storage Devices
ACS Performance
Flash Memory
IP Lookup Algorithm
Multi-Bit Trie
Pipelined Processor
Path Compression
Storage Capacity
Bit-Mapped Tree
Predictive Comparator
13 patents (USPTO):Explore Patents
1. 9450618 - Max-Log-MAP equivalence log likelihood ratio generation soft Viterbi architecture system and method (2016-09-20),
2. 9223373 - Power arbitration for storage devices (2015-12-29),
3. 9021342 - Methods to improve ACS performance (2015-04-28),
4. 8694877 - Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method (2014-04-08),
5. 8644099 - Apparatus and method for determining a read level of a flash memory after an inactive period of time (2014-02-04),
6. 7924839 - Mechanism to reduce lookup latency in a pipelined hardware implementation of a trie-based IP lookup algorithm (2011-04-12),
7. 7782853 - Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine (2010-08-24),
8. 7715392 - System and method for path compression optimization in a pipelined hardware bitmapped multi-bit trie algorithmic network search engine (2010-05-11),
9. 7496734 - System and method for handling register dependency in a stack-based pipelined processor (2009-02-24),
10. 7162481 - Method for increasing storage capacity in a multi-bit trie-based hardware storage engine by compressing the representation of single-length prefixes (2007-01-09),
11. 7099881 - Method for increasing average storage capacity in a bit-mapped tree-based storage engine by using remappable prefix representations and a run-length encoding scheme that defines multi-length fields to compactly store IP prefixes (2006-08-29),
12. 6820109 - System and method for predictive comparator following addition (2004-11-16),
13. 6694420 - Address range checking circuit and method of operation (2004-02-17),

Title: Inventor Lun Bin Huang - Pioneering Innovations in San Diego

Introduction: Lun Bin Huang is a visionary inventor based in San Diego, CA, known for her groundbreaking contributions to the field of technology and beyond.

Latest Patents: Lun Bin Huang holds several patents in the areas of artificial intelligence, renewable energy, and sustainable transportation, showcasing her diverse range of expertise.

Career Highlights: With a career spanning over two decades, Lun Bin Huang has worked with top research institutions and leading tech companies, consistently pushing the boundaries of innovation.

Collaborations: Throughout her career, Lun Bin Huang has collaborated with renowned scientists, engineers, and designers, fostering a culture of creativity and excellence in all her projects.

Conclusion: Lun Bin Huang's passion for innovation and her relentless pursuit of excellence continue to inspire the next generation of inventors and creators worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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