Stmicroelectronics Gmbh

S-tec Corporation

Hgst Technologies Santa Ana, Inc.

Lun Bin Huang

Nicholas Julian Richardson

Suresh Rajgopal

Sivagnanam Parthasarathy

Alessandro Risso

Aldo Giovanni Cometti

Razak Hossain

Dillip Kumar Dash

Ashot Melik-Martirosian

Umang Thakkar

Amir Alavi

A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.

Max-Log-MAP equivalence log likelihood ratio generation soft Viterbi architecture system and method

Aspects of the subject disclosure relate to a storage device including a flash memory, a controller coupled to the flash memory, wherein the controller is configured to store data to the flash memory and a power arbiter unit coupled to the controller and to the flash memory via a plurality of flash channels, wherein the power arbiter unit is configured to receive a plurality of power requests via one or more of the plurality of flash channels and process the plurality of power requests based on a respective priority identifier associated with each of the plurality of power requests. Additionally, a computer-implemented method and power arbiter unit (PAB) are provided.

Power arbitration for storage devices

In one embodiment, systems and methods of operating a SOVA system is disclosed that comprises determining the start and stop values for a trellis tree and using the start and stop values to determine the initial states of a plurality of branches within the trellis tree.

Methods to improve ACS performance

Max-log-map equivalence log likelihood ratio generation soft viterbi architecture system and method

Disclosed is an apparatus and method for determining a dwell time in a non-volatile memory circuit after a shutdown of the memory circuit. A voltage shift is calculated by comparing a first read level voltage required to read a test block stored before the shutdown and a second read level voltage required to read a second test block stored after the shutdown. A shutdown time is determined from a look up table indexed by the voltage shift and a number of program/erase cycles. The dwell time is calculated as a function of the drive temperature, a clock, and a block time stamp. Once the dwell time is calculated, a controller calculates a new read level voltage based, in part, on the dwell time and provides one or more programming commands representative of the new read level voltage to the memory circuit to read the memory circuit.

Apparatus and method for determining a read level of a flash memory after an inactive period of time

A series of hardware pipeline units each processing a stride during prefix search operations on a multi-bit trie includes, within at least one pipeline unit other than the last pipeline unit, a mechanism for retiring search results from the respective pipeline unit rather than passing the search results through the remaining pipeline units. Early retirement may be triggered by either the absence of subsequent strides to be processed or completion (a miss or end node match) of the search, together with an absence of active search operations in subsequent pipeline units. The early retirement mechanism may be included in those pipeline units corresponding to a last stride for a maximum prefix length shorter than the pipeline (e.g., 20 or 32 bits rather than 64 bits), in pipeline units selected on some other basis, or in every pipeline unit. Worst-case and/or average latency for prefix search operations is reduced.

Mechanism to reduce lookup latency in a pipelined hardware implementation of a trie-based IP lookup algorithm

A multi-bit trie network search engine is implemented by a number of pipeline logic units corresponding to the number of longest-prefix strides and a set of memory blocks for holding prefix tables. Each pipeline logic unit is limited to one memory access, and the termination point within the pipeline logic unit chain is variable to handle different length prefixes. The memory blocks are coupled to the pipeline logic units with a meshed crossbar and form a set of virtual memory banks, where memory blocks within any given physical memory bank may be allocated to a virtual memory bank for any particular pipeline logic unit. An embedded programmable processor manages route insertion and deletion in the prefix tables, together with configuration of the virtual memory banks.

Apparatus and method of using fully configurable memory, multi-stage pipeline logic and an embedded processor to implement multi-bit trie algorithmic network search engine

For use in a pipeline network search engine of a router, a path compression optimization system and method is disclosed for eliminating single entry trie tables. The system embeds in a parent trie table (1) path compression patterns that comprise common prefix bits of a data packet and (2) skip counts that indicate the length of the path compression patterns. The network search engine utilizes the path compression patterns and the skip counts to eliminate single entry trie tables from a data structure. Each path compression pattern is processed one stride at a time in subsequent pipeline stages of the network search engine. The elimination of unnecessary single entry trie tables reduces memory space, power consumption, and the number of memory accesses that are necessary to traverse the data structure.

System and method for path compression optimization in a pipelined hardware bitmapped multi-bit trie algorithmic network search engine

There is disclosed a data processor comprising 1) a register stack comprising a plurality of architectural registers that stores operands required by instructions executed by the data processor; 2) an instruction execution pipeline comprising N processing stages, where each processing stage performs one of a plurality of execution steps associated with a pending instruction being executed by the instruction execution pipeline; and 3) at least one mapping register associated with at least one of the N processing stages, wherein the at least one mapping register stores mapping data that may be used to determine a physical register associated with an architectural stack register accessed by the pending instruction.

System and method for handling register dependency in a stack-based pipelined processor

Prefixes terminating with end node entries each containing identical length prefix portions in a single child table are compressed by replacing the end node entries with one or more compressed single length (CSL) prefix entries in the child table that contain a bitmap for the prefix portions for the end node entries. A different type parent table trie node entry is created for the child table. Where the prefix portions are of non-zero length, the parent table contains a bitmap indexing the end node entries. Where the prefix portions are of length zero, the parent table may optionally contain a bitmap for the prefix portions, serving as an end node. The number of prefix portions consolidated within the CSL node entry is based upon the prefix portion length.

Method for increasing storage capacity in a multi-bit trie-based hardware storage engine by compressing the representation of single-length prefixes

Sparsely distributed prefixes within a bitmapped multi-bit trie are compressed by one or more of: replacing a single entry table string terminating with a single prefix end node with a parent table entry explicitly encoding a prefix portion; replacing a table with only two end nodes or only an end node and an internal node with a single parent table entry explicitly encoding prefix portions; replacing two end nodes with a single compressed child entry at a table location normally occupied by an internal node and explicitly encoding prefix portions; and replacing a plurality of end nodes with a prefix-only entry located at the table end explicitly encoding portions of a plurality of prefixes. The compressed child entry and the prefix-only entry, if present, are read by default each time the table is searched. Run length encoding allows variable length prefix portions to be encoded.

Method for increasing average storage capacity in a bit-mapped tree-based storage engine by using remappable prefix representations and a run-length encoding scheme that defines multi-length fields to compactly store IP prefixes

A computing system includes a plurality of full adders that each receives a bit-wise inversion of a bit of a first data, a bit of a second data, and a bit of a third data, respectively, and provides a sum output and a carry output. An exclusive-OR logic module receives the sum output of a first of the plurality of full adders and a carry output of a second of the plurality of full adders and provides an exclusive-OR output. An AND logic module has a plurality of inputs and an AND output, wherein the exclusive-OR output is electrically connected to one of the plurality of inputs of the AND logic module, and the AND output provides a signal that indicates whether the first data equals the sum of the second data and third data.

System and method for predictive comparator following addition

An address range checking circuit capable of determining if a target address, A&lsqb;M:0&rsqb;, is within an address space having 2 address locations beginning at a base address location, B&lsqb;M:0&rsqb;, is disclosed, wherein the address range checking circuit does not require a large comparator circuit. The address range checking circuit comprises: 1) comparison circuitry for determining if the address segment A&lsqb;N&minus;1:0&rsqb; is less than the address segment B&lsqb;N&minus;1:0&rsqb; and generating on a first control signal; 2) first equivalence detection circuitry for determining if the address segment A&lsqb;M:N&rsqb; is equal to the address segment B&lsqb;M:N&rsqb; and generating an A&equals;B status signal; 3) second equivalence detection circuitry for determining if the address segment A&lsqb;M:N&rsqb; is equal to the address segment B&lsqb;M:N&rsqb; plus one and generating an A&equals;B&plus;1 status signal; and 4) a multiplexer that outputs the A&equals;B status signal or the A&equals;B&plus;1 status signal depending on the value of the first control signal.

Growing community of inventors

San Diego, CA, United States of America

Lun Bin Huang