Warren, NJ, United States of America

Louis C Parrillo

This inventor holds 10 USPTO granted patents. Top assignees: At&t Bell Laboratories, American Telephone & Telegraph Co., At&t Bell Laboratories, Bell Telephone Laboratories. Active years: 1984-1988.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Louis C Parrillo. Retrieved from https://idiyas.com/inventor/louis-c-parrillo-40apae2n

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.1

ph-index = 8

Forward Citations = 266(Granted Patents)


Company Filing History:


Years Active: 1984-1988

Loading Chart...
10 patents (USPTO):Explore Patents

Title: **Louis C Parrillo - Innovator in CMOS Technology**

Introduction

Louis C Parrillo is a notable inventor based in Warren, NJ, known for his contributions to the field of complementary metal-oxide-semiconductor (CMOS) technology. With a remarkable portfolio of 10 patents, Parrillo has focused on enhancing the performance and reliability of CMOS devices, particularly in preventing latchup, a critical issue in semiconductor design.

Latest Patents

Parrillo's recent patents reflect his innovative approach to CMOS technology. One of his significant inventions, titled "Methods for fabricating latchup-preventing CMOS device," introduces a novel device structure that maximizes the spacing between n-channel and p-channel FETs to less than 10 µm while preventing latchup. This device features a substrate with a heavily doped bulk region and a thin, moderately doped layer, incorporating a polysilicon-filled trench between the two types of FETs. The design effectively reduces the risk of latchup by utilizing a heavily doped region connected to the trench.

Another important patent by Parrillo is "Method for preventing latchup in CMOS devices," which outlines a method to form a CMOS structure that minimizes lateral resistance in the n-tub, effectively reducing the likelihood of latchup. By employing proton bombardment to create a retrograde n+ region in the n-tub, Parrillo's method significantly enhances performance without disrupting standard CMOS processing steps. This innovative technique harnesses a beam of hydrogen ions or doubly ionized helium to achieve the desired results.

Career Highlights

Throughout his career, Louis C Parrillo has made significant strides in the advancement of semiconductor technology. He.has held positions at prestigious organizations such as AT&T Bell Laboratories and American Telephone & Telegraph Company (AT&T). His work in these influential companies has allowed him to contribute directly to the development and optimization of CMOS devices.

Collaborations

Parrillo has collaborated with esteemed colleagues in the field, including William T Lynch and Gerald A Coquin. These partnerships have played a vital role in driving innovation and fostering new ideas in CMOS technology.

Conclusion

Louis C Parrillo stands out as a significant figure in semiconductor innovation, with a particular focus on CMOS technology. His ten patents demonstrate his commitment to resolving critical challenges in device performance and reliability. As the industry continues to evolve, Parrillo's work will undoubtedly leave a lasting impact on the future of electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…