The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 1987
Filed:
Apr. 21, 1986
William T Lynch, Summit, NJ (US);
Louis C Parrillo, Warren, NJ (US);
AT&T Bell Laboratories, Murray Hill, NJ (US);
Abstract
A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the device, is disclosed. The inventive CMOS device includes a latchup-preventing, polysilicon-filled trench formed in the semiconductor substrate between the n- and p-channel FETs of the device. The polysilicon-filled trench is essentially free of crack-inducing voids, and achieves a width less than 10 .mu.m, because the angle between the trench sidewall and a perpendicular drawn to the substrate surface is greater than, or equal to, about 5 degrees but less than about 10 degrees. Also, a thickness of the polysilicon deposited into the trench is greater than half the width of the trench.