Hsinchu, Taiwan

Leo Li

This inventor holds 1 USPTO granted patent and 4 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Leo Li. Retrieved from https://idiyas.com/inventor/leo-li-vb53y1pa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Leo Li and Semiconductor Packaging Innovation.

Introduction

Leo Li is an inventor based in Hsinchu, Taiwan. His patent work concerns advanced semiconductor packaging, including structures that integrate semiconductor dies and spacer dies on an interposer.

Latest Patents

The provided information lists one patent for Leo Li: “Chip-on-wafer-on-board structure using spacer die and methods of forming the same.” The disclosed structure includes an interposer with bump structures, semiconductor dies bonded to one subset of the bumps, and spacer dies bonded to another subset. A molding compound die frame surrounds the dies. The semiconductor dies contain transistors and metal interconnect structures, while the spacer dies are transistor-free. This arrangement describes an approach to semiconductor integration and packaging.

Career Highlights

Li is associated with Taiwan Semiconductor Manufacturing Company Limited. His listed patent count is 1 patent, reflecting the single patent provided in the supplied information.

Collaborations

The supplied information identifies Sheng-Kai Chang as Li’s coworker. The patent details provided do not specify the coworker’s role or confirm their participation in this invention.

Conclusion

Leo Li’s listed patent focuses on a chip-on-wafer-on-board packaging structure that uses spacer dies alongside semiconductor dies, highlighting an approach to organizing components within an interposer-based assembly.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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