The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 29, 2026

Filed:

Jun. 24, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsinchu, TW;

Inventors:

Sheng-Kai Chang, Taipei City, TW;

Leo Li, Hsinchu, TW;

Chung-Hsien Hun, Zhubei City, TW;

Lieh-Chuan Chen, Hsinchu City, TW;

Chien-Li Kuo, Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2023.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/65 (2026.01); H10W 70/695 (2026.01); H10W 72/00 (2026.01); H10W 74/01 (2026.01); H10W 90/00 (2026.01); H10W 70/685 (2026.01); H10W 74/00 (2026.01); H10W 74/15 (2026.01); H10W 74/40 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/093 (2026.01); H10W 70/611 (2026.01); H10W 70/65 (2026.01); H10W 70/695 (2026.01); H10W 72/0198 (2026.01); H10W 74/014 (2026.01); H10W 74/016 (2026.01); H10W 74/019 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 70/685 (2026.01); H10W 74/00 (2026.01); H10W 74/15 (2026.01); H10W 74/40 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

A semiconductor structure may include an interposer including on-interposer bump structures, at least one semiconductor die bonded to a first subset of the on-interposer bump structures through first solder material portions, at least one spacer die bonded to a second subset of the on-interposer bump structures through second solder material portions, and a molding compound die frame laterally surrounding each of the at least one semiconductor die and the at least one spacer die. Each of the at least one semiconductor die includes a respective set of transistors and a respective set of metal interconnect structures. Each of the at least one spacer die is free from any transistor therein.


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