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For the Inventor, By the Inventor

Laguna Hills, CA, United States of America

L Randall Mote, Jr

This inventor holds 16 USPTO granted patents. Top assignees: Samsung Electronics Co., Ltd., Ast Research, Inc., Broadcom Corporation. Active years: 1994-2007.

IDiyas Innovation Intelligence. (2026). Inventor Profile: L Randall Mote, Jr. Retrieved from https://idiyas.com/inventor/l-randall-mote-jr

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 16

% Patents Active = 100.0

Average Co-Inventor Count = 1.1

ph-index = 12

Forward Citations = 535(Granted Patents)


Company Filing History:

goldMedal10 out of 132,108 
 
Samsung Electronics Co., Ltd.
 patents
silverMedal4 out of 173 
 
Ast Research, Inc.
 patents
bronzeMedal2 out of 11,124 
 
Broadcom Corporation
 patents

Years Active: 1994-2007

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16 patents (USPTO):Explore Patents
1. 7165193 - Efficient memory allocation scheme for data collection (2007-01-16),
2. 6836861 - Efficient memory allocation scheme for data collection (2004-12-28),
3. 5852617 - Jtag testing of buses using plug-in cards with Jtag logic mounted thereon (1998-12-22),
4. 5826043 - Docking station with serially accessed memory that is powered by a (1998-10-20),
5. 5815673 - Method and apparatus for reducing latency time on an interface by (1998-09-29),
6. 5805609 - Method and apparatus for testing a megacell in an ASIC using JTAG (1998-09-08),
7. 5764966 - Method and apparatus for reducing cumulative time delay in synchronizing (1998-06-09),
8. 5731715 - Glitch-free clock enable circuit (1998-03-24),
9. 5666494 - Queue management mechanism which allows entries to be processed in any (1997-09-09),
10. 5654929 - Refresh strategy for DRAMs (1997-08-05),
11. 5648973 - I/O toggle test method using JTAG (1997-07-15),
12. 5638534 - Memory controller which executes read and write commands out of order (1997-06-10),
13. 5631912 - High impedance test mode for JTAG (1997-05-20),
14. 5630110 - Method and apparatus for enhancing performance of a processor (1997-05-13),
15. 5537062 - Glitch-free clock enable circuit (1996-07-16),

Title: L Randall Mote, Jr: Innovator in Efficient Memory Allocation

Introduction

L Randall Mote, Jr. is a notable inventor based in Laguna Hills, CA (US). He has made significant contributions to the field of integrated circuits, holding a total of 16 patents. His work focuses on enhancing hardware efficiency and reducing manufacturing costs.

Latest Patents

One of his latest patents is titled "Efficient Memory Allocation Scheme for Data Collection." This innovative system and method provide an integrated circuit that includes a small on-chip buffer to store collected data. By shifting the burden of storing the majority of the collected data to external system memory, which typically consists of commodity memory chips, he has increased overall hardware efficiency. This approach also helps achieve lower ASIC manufacturing costs.

Career Highlights

Throughout his career, L Randall Mote, Jr. has worked with prominent companies such as Samsung Electronics Co., Ltd. and Ast Research, Inc. His experience in these organizations has allowed him to develop and refine his innovative ideas in the field of memory allocation and integrated circuits.

Collaborations

Some of his notable coworkers include Joey Y Chen and Thuji Simon Lin. Their collaboration has contributed to the advancement of technology in their respective fields.

Conclusion

L Randall Mote, Jr. continues to be a significant figure in the realm of innovations related to memory allocation and integrated circuits. His contributions have paved the way for more efficient hardware solutions in the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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