The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 1997

Filed:

Dec. 19, 1995
Applicant:
Inventor:

L Randall Mote, Jr, Laguna Hills, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R / ;
U.S. Cl.
CPC ...
371 223 ; 371 225 ;
Abstract

A specially configured JTAG test circuit allows multiple bus connections within an integrated circuit chip to be selectively placed in a high impedance state in an efficient manner. The output enable shift register locations are placed in close logical proximity to one another along the JTAG data shift register boundary scan path so that data bits need not be shifted into all of the data shift register locations within the integrated circuit chip in order to selectively enable and disable the several bus interfaces within the integrated circuit chip. In this manner, the integrated circuit chip may be isolated from selected ones of the buses connected to the integrated circuit chip, while other bus connections can remain enabled to drive others of the buses connected to the integrated circuit chip. Thus, problems associated with setting the entire integrated circuit chip in a high impedance mode are avoided.


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