The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 1998

Filed:

Jul. 15, 1996
Applicant:
Inventor:

L Randall Mote, Jr, Laguna Hills, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
326 93 ; 327141 ;
Abstract

A circuit utilizes a toggle flip-flop, a D flip-flop and combinatorial logic to generate a clock signal which can be enabled or disabled without creating spikes or shortened pulses in the clock signal. The circuit receives an input clock signal and an input clock enable signal. The circuit generates an output clock signal which is an enabled/disabled version of the input clock signal, controlled by the input clock enable signal. The circuit thus provides the operational advantages of enabling or disabling, with a single control signal, groups of logic circuits triggered by a common clock signal.


Find Patent Forward Citations

Mote, Jr, L. (1998). Glitch-free clock enable circuit (U.S. Patent No. 5731715). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5731715

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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