Tainan, Taiwan

Kun Ching Chen

This inventor holds 1 USPTO granted patent. Top assignee: Advanced Semiconductor Engineering, Inc.. Active years: 2003.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kun Ching Chen. Retrieved from https://idiyas.com/inventor/kun-ching-chen-4lap4jng

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2003

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1 patent (USPTO):Explore Patents

Title: Kun Ching Chen: Innovator in Semiconductor Packaging

Introduction

Kun Ching Chen is a notable inventor based in Tainan, Taiwan. He has made significant contributions to the field of semiconductor packaging, showcasing his innovative spirit through his patented inventions.

Latest Patents

Kun Ching Chen holds a patent for a substrate strip and its manufacturing method. This invention involves a substrate strip that includes multiple substrate units, each designed for packaging a semiconductor package. The substrate strip features a frame with at least one opening, at least one first substrate unit integrally formed with the strip frame, and at least one second substrate unit securely attached to the strip frame by an adhesive. The method for creating this substrate strip includes separating defected substrate units and securely attaching accepted units back to the strip.

Career Highlights

Kun Ching Chen is currently employed at Advanced Semiconductor Engineering, Inc., where he applies his expertise in semiconductor technology. His work has contributed to advancements in the efficiency and reliability of semiconductor packaging.

Collaborations

Some of his coworkers include Yi Chuan Ding and Yung I Yeh, who collaborate with him on various projects within the semiconductor industry.

Conclusion

Kun Ching Chen's innovative contributions to semiconductor packaging highlight his role as a key inventor in the field. His patent reflects a commitment to improving technology and efficiency in semiconductor manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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