Nantou, Taiwan

Ko-Ting Chen

This inventor holds 4 USPTO granted patents and 2 published patent applications. Top assignee: United Microelectronics Corp.. Active years: 2007-2009.

USPTO Granted Patents = 4 

% Patents Active = 100.0

Average Co-Inventor Count = 3.2

ph-index = 2

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2007-2009

Loading Chart...
4 patents (USPTO):Explore Patents

Title: Innovations of Ko-Ting Chen in Semiconductor Manufacturing

Introduction

Ko-Ting Chen is a notable inventor based in Nan-Tou Hsien, Taiwan. He has made significant contributions to the field of semiconductor manufacturing, holding a total of 4 patents. His work focuses on methods that enhance the efficiency and reliability of integrated circuits.

Latest Patents

One of his latest patents is a method of reducing charging damage to integrated circuits during semiconductor manufacturing. This invention involves an integrated circuit die that includes a first device region, a second device region, and a non-active region. A first implant mask is formed over the semiconductor substrate, covering the second device region and the non-active region while exposing the first device region. Dopant species are implanted into the exposed semiconductor substrate within the first device region to create first doping regions. A second implant mask is then formed, covering the first device region while exposing the second device region and a portion of the non-active region. This allows for the implantation of dopant species into the second active device region, forming second doping regions.

Another patent by Ko-Ting Chen also addresses the reduction of charging damage during semiconductor manufacturing. In this method, a semiconductor substrate with an integrated circuit die area surrounded by a scribe lane is utilized. Within the die area, a first trench isolation region and a second trench isolation region are formed. The first trench isolation region isolates a first active device region from a second active device region, while the second trench isolation region includes trench dummy features to reduce loading effects. A first gate electrode is formed on the first active device region, and a second gate electrode is formed on the second active device region. The first active device region is masked, allowing for an ion implantation process to implant dopant species into the second active device region.

Career Highlights

Ko-Ting Chen is currently employed at United Microelectronics Corporation, a leading company in the semiconductor industry. His work has been instrumental in advancing technologies that improve the performance of integrated circuits.

Collaborations

Throughout his career, Ko-Ting Chen has collaborated with notable colleagues, including Wen-Bin Lu and Chao-Hu Liang. These collaborations have contributed to the development of innovative solutions in semiconductor manufacturing.

Conclusion

Ko-Ting Chen's contributions to semiconductor manufacturing through his patents demonstrate his expertise and commitment to innovation in the field. His work continues to

This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to [email protected]
Loading…