This inventor holds 3 USPTO granted patents and 6 published patent applications. Top assignee: Volantis Semiconductor Inc.. Active years: 2026.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2026
Title: Kevin Nan Lam: Advancing Wafer-Scale Integration and Power Delivery
Introduction
Kevin Nan Lam is an inventor based in Pleasanton, California. His patent work addresses wafer-scale integration, semiconductor packaging, and power delivery. He is associated with Volantis Semiconductor Inc. and holds 3 patents.
Latest Patents
Lam’s recent patent work includes “Back Side Power Delivery for Wafer-Scale Integration with Solderless Modular Power Substrates.” The disclosed techniques connect modular power substrates to the back side of a wafer-scale silicon interposer using compression connectors and force from a unified control board. The board’s DC-to-DC converters deliver power through the substrates and through-silicon vias to functional chips bonded to the interposer.
Another recent patent is “Wafer-Scale Integration with a Stiffening Isometric Grid Array.” It describes reinforcing a wafer-scale silicon interposer with an isometric grid array while keeping its back side accessible through open recesses. Modular power substrates can then be attached through those recesses and connected to a unified control board, which supplies power to the functional chips through the substrates and through-silicon vias.
Career Highlights
Lam’s disclosed inventions focus on combining mechanical support and electrical power delivery in wafer-scale semiconductor systems. The approaches pair interposers, functional chips, modular power substrates, and control-board components to support integrated designs.
Collaborations
Lam is associated with Volantis Semiconductor Inc. His coworker, Tapabrata Ghosh, is also identified in the provided information.
Conclusion
Kevin Nan Lam’s patent portfolio highlights engineering approaches to stiffening wafer-scale interposers and delivering power to integrated functional chips.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile