Hsinchu, Taiwan

Ke-Gang Wen

This inventor holds 4 USPTO granted patents and 23 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ke-Gang Wen. Retrieved from https://idiyas.com/inventor/ke-gang-wen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 4 

% Patents Active = 100.0

Average Co-Inventor Count = 4.6

ph-index = 1


Company Filing History:


Years Active: 2026

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4 patents (USPTO):Explore Patents

Title: Ke-Gang Wen: Innovator in Semiconductor Technology

Introduction

Ke-Gang Wen is an inventor based in Hsinchu, Taiwan. He is known for his contributions to semiconductor technology, focusing on innovative device structures and methods of fabrication. Although he currently holds no granted patents, his work in the field is noteworthy.

Latest Patent Applications

Ke-Gang Wen has filed several significant patent applications. One of his latest applications is for a "SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME." This application describes a semiconductor device structure that includes a through silicon via disposed through a dielectric material, an interconnection structure, and a substrate. The design features a top surface of the through silicon via with a first diameter that is substantially greater than the second diameter located in the substrate. Additionally, the structure includes an alloy portion surrounding the through silicon via, a barrier layer surrounding the alloy portion, and a liner surrounding the barrier layer, all contributing to a funnel-shaped cross-section.

Another notable application is for an "Interconnect Structure for Front-to-Front Stacked Chips." This application discloses interconnect structures for front-to-front stacked chips and methods of fabrication. The exemplary system on integrated circuit (SoIC) includes a first die that is front-to-front bonded with a second die. This bonding is achieved by connecting the topmost metallization layers of both dies. The application also details a through via that extends partially through the first die's frontside multilayer interconnect, through a device layer, and through a backside power rail, which may be part of a backside multilayer interconnect.

Conclusion

Ke-Gang Wen is an innovative inventor whose work in semiconductor technology showcases his potential to contribute significantly to the field. His latest patent applications reflect a commitment to advancing device structures and interconnect methods, highlighting his role in the ongoing evolution of semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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