The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 25, 2026

Filed:

Nov. 17, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ke-Gang Wen, Hsinchu County, TW;

Kuan-Hsun Wang, Hsinchu City, TW;

Tsung-Chieh Hsiao, Changhua County, TW;

Liang-Wei Wang, Hsinchu City, TW;

Dian-Hau Chen, Hsinchu, TW;

Hsin-Feng Chen, Yilan City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/20 (2026.01); H10W 20/40 (2026.01); H10W 20/41 (2026.01); H10W 72/90 (2026.01); H10W 90/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 20/20 (2026.01); H10W 20/212 (2026.01); H10W 20/2125 (2026.01); H10W 20/2134 (2026.01); H10W 20/40 (2026.01); H10W 20/41 (2026.01); H10W 90/00 (2026.01); H10W 72/952 (2026.01); H10W 90/297 (2026.01); H10W 90/722 (2026.01);
Abstract

A semiconductor structure includes a substrate, a device layer over the substrate, an interconnect structure over the device layer, and a first plurality of through vias and a second plurality of through vias extending through the substrate, the device layer, and the interconnect structure. The device layer includes first and second device regions. From a top view, the first device region has a first side facing and spaced apart from a second side of the second device region. From the top view, the first plurality of through vias are disposed along a third side of the first device region opposite to the first side of the first device region, the second plurality of through vias are disposed along a fourth side of the second device region opposite to the second side of the second device region. Each through via has a racetrack shape from the top view.


Find Patent Forward Citations

Loading…