Hsinchu, Taiwan

Kaun-Lun Cheng

This inventor holds 1 USPTO granted patent. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2007.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Kaun-Lun Cheng. Retrieved from https://idiyas.com/inventor/kaun-lun-cheng

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 22(Granted Patents)


Company Filing History:


Years Active: 2007

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1 patent (USPTO):Explore Patents

Title: Innovations by Kaun-Lun Cheng in Semiconductor Technology.

Introduction

Kaun-Lun Cheng is a notable inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of semiconductor technology, particularly in the development of methods to enhance charge carrier mobility in MOSFET devices.

Latest Patents

Cheng holds a patent titled "Method for selectively forming strained etch stop layers to improve FET charge carrier mobility." This innovative method involves creating a strained channel MOSFET device that enhances charge carrier mobility. The process includes providing first and second FET devices with opposite polarities on a substrate, forming a strained layer with selected stress types, and removing a portion of the strained layer to optimize performance.

Career Highlights

Cheng is currently employed at Taiwan Semiconductor Manufacturing Company Limited, where he continues to advance semiconductor technologies. His work has been instrumental in improving the efficiency and performance of FET devices.

Collaborations

Cheng collaborates with talented colleagues, including Shui-Ming Cheng and Yu-Yuan Yao, who contribute to the innovative environment at their workplace.

Conclusion

Kaun-Lun Cheng's contributions to semiconductor technology, particularly through his patented methods, highlight his role as a key innovator in the field. His work continues to influence advancements in electronic devices and systems.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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